mips-cpu-design

mips-cpu-design

Study in MIPS microarchitecture trade-offs implementing three CPU designs: single-cycle, hardware-scheduled multicycle, and software-scheduled pipelined core.

MIPS Python Verilog iastate

Github: https://github.com/conneroisu/mips-cpu-design

mips-cpu-design ΒΆ

A study in MIPS microarchitecture trade-offs through three distinct CPU implementations: a single-cycle design, a hardware-scheduled multicycle processor, and a software-scheduled pipelined core. I built each design in Verilog and used Python tooling to automate testing and compare performance characteristics across the three approaches. This project gave me hands-on experience reasoning about CPI, hazard handling, and the real costs of pipeline stages.

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